Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to data storage in computer systems. More particularly, the present invention relates to the manipulation of data that has been stored in random access memory during periods when the computer system is placed in a low power mode to minimize the latency that otherwise occurs when the system enters a low power mode and resumes operation from a low power mode.
2. Background of the Invention
Almost all computer systems include a processor and a system memory. The system memory functions as the working memory of the computer system, where data is stored that has been or will be used by the processor and other system components. The system memory typically includes banks of dynamic random access memory (DRAM) circuits. According to normal convention, a memory controller interfaces the processor to a memory bus that connects electrically to the DRAM circuits. The system memory provides storage for a large number of instructions and/or a large amount of data for use by the processor, providing faster access to the instructions and/or data than would otherwise be achieved if the processor were forced to retrieve data from a disk or drive.
Because system memory typically is constructed of dynamic random access memory circuits, the contents of the memory are volatile. To preserve the integrity of the data stored in system memory, a periodic refresh signal must be sent to each memory cell to refresh the voltage levels of each cell, where the data is stored. Failure to timely refresh the memory cells of system memory causes the data to be lost. Thus, when power is turned off to a volatile memory device, the contents of that memory are lost. Data that is to be stored long-term on a computer system thus is stored in other non-volatile memory devices. Most computer systems include a hard drive that is capable of permanently storing data on magnetic tape. Other removable drives, such as zip drives, CD-ROMs, DVD-ROMs, and the like, may also be used for long-term storage of data. In these types of media, the data is preserved, even when power is removed from the computer system.
Almost all portable computers, and some desktop computers, may be placed in a low power state to preserve power. Preservation of power is especially important in portable computers, where operating power may be provided from batteries. To extend the life of batteries in portable computers, and thus extend the amount of time that a user can operate a portable computer without recharging the batteries or finding an electrical source, most portable computers are capable of going into a sleep mode where minimal power is consumed. The sleep mode permits the computer system to be placed in standby, so that operation can resume when the user is ready, without requiring the system to boot.
As power management of portable computer systems has evolved, two different low power modes have been developed and used commercially. The first low power state is referred to as the xe2x80x9csuspendxe2x80x9d mode or xe2x80x9cSuspend to RAMxe2x80x9d mode. In the suspend mode, the system memory remains powered while the system is taken to a non-operational state. The advantage of keeping the system memory powered is that when operation is resumed, the system is ready within a very short period for operation, in the state last used by the operator. Thus, resuming from a suspend mode only takes a few seconds, because very little system context is moved. Suspend to RAM generally is preferred as a bookmark feature because of its xe2x80x9cinstant onxe2x80x9d low latency resume time. Suspend to RAM is also called the S1, S2, or S3 power state by the ACPI nomenclature.
Conventional Suspend to RAM works by stopping the clocks to the system, while leaving the entire system power on. Because the power used by the system depends on the system clock speeds, removing the clock signals significantly lowers the system power. Suspend to RAM often is referred to as xe2x80x9cPower on Suspend.xe2x80x9d When the system resumes operation from Suspend to RAM, the clocks may simply be started to restore system operation. Another form of Suspend to RAM stores the context of certain system devices to system memory. Examples of the device contexts that may be saved include peripherals such as audio controllers, the state of the processor, the contents of the processor cache, and the like. Once the context of these devices is stored to system memory, the clocks to those devices are stopped and power is removed. The system memory, however, remains powered to maintain its contents. To resume operation, the system BIOS or operating system restores the context of the peripherals from system memory, and then system operation is resumed.
The second low power mode is known as xe2x80x9chibernationxe2x80x9d or xe2x80x9chibernation to diskxe2x80x9d, which is referred to as the S4 power state by the ACPI nomenclature. In this mode, which is the lowest power mode of the computer system other than power-off, the computer system consumes minimal energy. The hibernation mode can be analogized to a no-power bookmark of the existing state of the computer system. When the hibernation mode is entered, the system hardware state is copied to the hard drive in a predetermined sequence. Because the hard drive is non-volatile memory, all power can then be removed from the system. Upon resume, the system is powered on, and control is given to the system ROM. A sequence called POST performs initial configuration of the system. During the POST sequence, the BIOS checks a bit in non-volatile memory to detect if the system had been placed in the hibernation state the last time system power was turned off. If the BIOS determines that it is resuming from a hibernation state, it will start to restore the system in a predetermined way. First, the system peripherals may be configured by reading the data from the hard drive. After system peripherals are configured, the system memory may be restored to the state that existed just prior to placing the system in hibernation. The BIOS algorithm will restore the system DRAM, filling DRAM memory in a predetermined sequence. After the entire state of the system has been restored by the ROM-based restoration algorithm, control of the system is handed to the operating system and the system user. Hibernation to disk thus allows the user to set a bookmark so that they can leave the system in a very low or no power state, and then return to the exact environment where they turned off the computer system. Because the context of the system is stored in non-volatile memory (on the hard drive), it provides reliable storage of the data in system memory, even during the low power state.
A delay period is encountered as the system context is stored to the hard drive, and again when the context is reloaded from the hard drive back to the system memory. The time required to access data from the hard drive is significantly longer than accessing data from system memory. Thus, there is a perceptible delay that occurs when data is loaded from the hard drive to the system memory after the hibernation mode is exited. This delay is exacerbated by increasingly large system memories. In many instances the suspend or resume process can require more than one minute to execute. This delay period is unworkable for systems that must be capable of instantly turning on to handle events.
Some have suggested that the data in system memory be compressed before hibernation occurs, to reduce the amount of data that must be copied and retrieved. Unfortunately, compression algorithms require extensive CPU power, and thus the act of compressing the system memory may actually require more time than simply writing uncompressed data to the hard drive. The Windows 2000 Operating System uses the knowledge of memory usage, so that unused areas of memory are not saved to disk during a hibernation event, as compared to previous systems, which typically stored the entire state of the memory, regardless of whether it contained valid data or context. Thus, this technique may reduce latency in suspend and resume operations, but only if the system memory has not been used substantially.
Conventional Hibernation to Disk is implemented by powering down the system in response to a system event. The system event can be the manual selection of an icon or menu entry, the selection of one or more keys, or system inactivity. Because the hibernation mode results in the removal of power, the context of all system peripherals is read and then stored to the hard drive. Next, the contents of the system memory are copied to the hard drive. A hard drive file that is equal to the size of the memory to be stored is created, which holds a mirror image of the system memory. After the contents of system memory are backed up, a flag is set in non-volatile memory indicating that the system context has been completely saved. Once the flag is set, the power is removed causing the contents of volatile memory (such as DRAM and the context of peripheral devices) to be lost. When the system resumes operation, the system BIOS or operating system polls the non-volatile flag bit that indicates that the hard drive contains valid system context. If the flag bit is set, the BIOS or operating system restores the system context from the hard drive before resuming system operation.
While the BIOS restoration algorithm is cognizant of the amount of system memory in the system, it has no knowledge of how extensively the operating system uses system memory. Thus, it is possible that the operating system has made very little or no use of system memory. For example, if the prior boot used a small, simple application, less than 10 MB of memory context may have been used. The BIOS restoration algorithm would, nonetheless, save and restore the entire amount of memory installed is the computer system was placed in a hibernation mode.
In addition, the time for a traditional store to disk does not start until the hibernation sequence is initiated. The operating system could have been idle for hours before the sequence was initiated, but because the sequence is performed automatically, the time needed for hibernation may be lengthy. In the case of a hibernation to disk initiated from a critical low battery condition, the inaccuracy of the fuel gauge may mean the system will exhaust its power before the hibernation sequence is finished (causing lost work or data). Thus, currently, the hibernation algorithm does not take proactive steps prior to the actual initiation of the hibernation sequence that could minimize the amount of time to conduct the hibernation to disk. In addition, the hibernation algorithm does not prioritize the data being saved.
For resume from hibernation, the length of time from when the system is turned on until it is usable is determined by the amount of memory stored. The resume sequence may force the user to wait while invalid or low priority data is restored to system memory. Thus, the restoration algorithm does not prioritize the data being restored to system memory.
It would be advantageous if memory that is not used is not stored or restored by the hibernation sequence. It also would be advantageous if the time required to hibernate the system to disk is reduced by keeping an image of the system context mirrored on the hard drive. Additionally, it would be desirable if the system could selectively decide that some of the system memory may not be hibernated, and should remain powered during a hibernation. Further, it would be advantageous if the time to restore the system to a usable state is shortened by restoring the system memory in an intelligent order.
Despite the deficiencies of the current hibernation and restoration algorithms, to date no one has developed a hibernation and restoration sequence that overcomes these problems.
The present invention solves the deficiencies of the prior art by configuring a computer system to support a fast hibernation mode of operation that saves power, while also minimizing the amount of time it takes to enter the hibernation mode, and to resume normal operations. The system periodically stores data from system memory to non-volatile memory, such as a hard disk drive, during normal operations when the system is idle. The system includes hardware activity monitors in the memory controller, CPU, or some other device that detect when the data in memory pages is changed. According to the preferred embodiment, a monitor is provided for each page, although other variations are possible. The monitor includes a number of dedicated bits or flags, including a dirty bit that indicates when the memory page has been the target of a write transaction. The fast hibernation algorithm periodically sweeps the activity monitors, and performs save operations to the non-volatile memory if the dirty bit has been set, indicating that the data has been altered. When the system enters hibernation mode, the algorithm determines which memory pages have been changed since the last save operation, and then saves those pages to memory. When resuming from the instantaneous hibernation mode, the algorithm checks the status of status bits in a control register that indicates which pages have been saved to disk, and restores those pages.
According to another embodiment of the present invention, the system is configured to support an instantaneous hibernation mode of operation. The system periodically stores data from system memory to non-volatile memory, such as a hard disk drive, during normal operations when the system is idle. The system includes hardware activity monitors in the memory controller, CPU or some other device that detect when the data in memory pages is changed. According to the preferred embodiment, a monitor is provided for each page, although other variations are possible. The monitor includes a number of dedicated bits or flags, including a dirty bit that indicates when the memory page has been the target of a write transaction. The fast hibernation algorithm periodically sweeps the activity monitors, and performs save operations to the non-volatile memory if the dirty bit has been set, indicating that the data has been altered. When the system enters an instantaneous hibernation mode, the algorithm checks the dirty bits and selectively supplies power to the memory pages that have not been saved since the last save operation. To implement this, independent switches under the control of the CPU of memory controller selectively turn off power to unsaved memory pages. When resuming from the instantaneous hibernation mode, the algorithm checks the status of status bits in a control register that indicates which pages have been saved to disk, and restores those pages.
According to another embodiment of the present invention, the system can also implement a fast resume procedure by restoring the memory pages that have the highest priority, and saving the other pages in the background, or as needed by the system devices. Prior to entering the hibernation mode, the pages may be prioritized based on various factors, including the last pages used, the pages used most frequently, or the pages that store the most critical data. The priority data may be saved to the control register or to any other suitable register. When power is resumed, the algorithm checks the priority data, and immediately restores the page or pages with the highest priority from the non-volatile memory. Other pages are subsequently restored in the background of other operations during idle time, or when data in unrestored pages is accessed.
These and other aspects of the present invention will become apparent upon analyzing the drawings, detailed description and claims, which follow.